1. Field of the Invention
The present invention relates to a memory cell and a nonvolatile semiconductor memory device provided with the same, and in particular to a memory cell allowing write and erase with a low voltage power supply as well as a nonvolatile semiconductor memory device provided with the memory cell.
2. Description of the Background Art
Recently, a flash memory which is a kind of nonvolatile semiconductor memory device has been expected as a memory device on the next generation because it can be manufactured at a lower cost than a dynamic random access memory (DRAM).
A memory cell array of a nonvolatile semiconductor memory device in the prior art will now be described below with reference to FIG. 43. A memory cell array 1000 of a NOR-type flash memory shown in FIG. 43 is provided with a plurality of word lines WL and a plurality of bit lines BL. FIG. 43 representatively shows only word lines WL1, WL2, WL3, . . . and bit lines BL1, BL2, BL3, . . . A memory cell MC is arranged at each of crossings between word lines WL and bit lines BL. The memory cell MC is formed of a MOS transistor of a floating type.
A structure of the memory cell transistor forming the memory cell will now be described below with reference to FIG. 44.
As shown in FIG. 44, the memory cell transistor includes an n-type source region 2 and an n-type drain region 3 which are formed at a main surface of a p-type semiconductor substrate 1, a floating gate electrode 5 which is formed on a channel region defined between source and drain regions 2 and 3 with a tunnel oxide film 4 therebetween, and a control gate electrode 7 formed on floating gate electrode 5 with an insulating film 6 therebetween. Source and drain regions 2 and 3 of each memory cell transistor are formed by ion implantation using a mask which is formed of a side wall insulating film 9 formed on side walls of floating gate electrode 5 and control gate electrode 7.
Referring to FIGS. 43 and 44, a source line SL is connected to source region 2 in each memory cell. Bit line BL is connected to drain region 3. Word line WL is connected to control gate electrode 7. A conductance between the source and drain varies depending on the potential applied to control gate electrode 7. A current starts to flow between the source and drain when the potential on control gate electrode 7 increases to a certain value, which is called a threshold. The threshold increases with increase in quantity of electrons accumulated in floating gate electrode 5.
The memory cell transistor stores information by changing the charged state of floating gate electrode 5. Since floating gate electrode 5 is electrically isolated from the surrounding by the insulating film, information is stored in a nonvolatile manner.
Read, write and erase operations of the NOR-type flash memory will be briefly described below.
In the write operation, electrons are injected into the floating gate electrode by channel hot electron injection. Thereby, a threshold voltage Vth of the memory cell transistor changes from a lower threshold side to a higher threshold side.
In the erase operation, electrons are extracted from a FN (Fowler-Nordheim) tunnelling phenomenon at a gate edge of the source or drain. Thereby, threshold voltage Vth changes from the higher threshold side to the lower threshold side.
In the read operation, a voltage of about 1 volt is applied to selected bit line BL, and an external power supply voltage Vcc is applied to selected word line WL so that information is read out depending on whether a current flows between the source and drain of the memory cell transistor located at the crossing between selected word line WL and selected bit line BL.
A threshold voltage distribution of the NOR-type flash memory will now be described below with reference to FIGS. 45 and 46. In NOR-type flash memory, as shown in FIG. 45, a state that threshold voltage Vth is higher than external power supply voltage Vcc (5 V) is called a written state, and a state that threshold voltage Vth is lower than external power supply voltage Vcc (5 V) is called an erased state.
In the NOR-type flash memory, writing is effected on one bit at a time, and erasing is effect on all the bits at a time. Therefore, the threshold voltage distribution in the erased state is wider than the threshold voltage distribution in the written state.
As shown in FIG. 46, when using external power supply voltage Vcc of 3.3 V, which is now widely used, a so-called overerased cell, in which threshold voltage Vth takes on the value of 1.5 V or less, appears.
A problem caused by the overerased cell in the flash memory will be described below with reference to FIG. 47. As shown in FIG. 47, it is assumed that data is to be read from memory cell MC1 connected to bit line BL, and memory cells MC2, MC3, MC4, . . . connected to the same bit line BL are overerased cells. For reading data from memory cell MC1, a voltage of about 1 V is applied to bit line BL. Further, external power supply voltage Vcc is applied to word line WL1 connected to memory cell MC1.
In this case, leak currents iO flows to bit line BL through the overerased cells in spite of the fact that word lines WL2, WL3, WL4, . . . connected to memory cells MC2, MC3, MC4, . . . bear the potentials of 0 V, respectively. As a result, selected memory cell MC1 which is actually in the written state is externally determined as it is in the erased state in spite of the fact that a current does not flow through memory cell MC1. Therefore, existence of these overerased cells results in a critical defect in the operation of the flash memory.
Then, description will be given on a DINOR-type flash memory in which bit lines are divided into sectors.
Contents of the DINOR-type flash memory in the prior art will now be described below.
The DINOR-type flash memory in the prior art has a memory cell array 2000 which will be described below with reference to FIG. 48. Memory cell array 2000 includes two memory cell array blocks BLK0 and BLK1 as shown in FIG. 48. FIG. 48 representatively shows only four memory cell transistors MC for each of memory cell array blocks BLK0 and BLK1.
Memory cell array block BLK0 includes memory cell transistors MC1a and MC1b each having a drain connected to a sub-bit line SBL1 as well as memory cell transistors MC2a and MC2b each having a drain connected to a sub-bit line SBL2. Further, memory cell array block BLK0 includes a select gate SG1 which opens and closes a connection between main bit line BL1 and sub-bit line SBL1, and a select gate SG2 which opens and closes a connection between main bit line BL2 and a sub-bit line SBL2.
Control gate electrodes of memory cell transistors MC1a and MC2a are connected to word line WL1, and control gate electrodes of memory cell transistors MC1b and MC2b are connected to word line WL2.
Memory cell transistors included in memory cell array block BLK0 are connected to source line SL1.
Likewise, memory cell array block BLK1 includes memory cell transistors MC3a and MC3b each having a drain connected to a sub-bit line SBL3, and memory cell transistors MC4a and MC4b each having a drain connected to a sub-bit line SBL4.
Memory cell array block BLK1 further includes a select gate SG3 which opens and closes a connection between main bit line BL1 and sub-bit line SBL3 as well as a select gate SG4 which opens and closes a connection between main bit line BL2 and sub-bit line SBL4.
Control gate electrodes of memory cell transistors MC3a and MC4a are connected to word line WL3, and control gate electrodes of memory cell transistors MC3b and MC4b are connected to word line WL4.
Memory cell transistors included in memory cell array block BLK1 are connected to source line SL2.
In the DINOR-type flash memory, write, erase and read operations for the memory cell are performed after selecting the corresponding memory cell array block by opening or closing the corresponding select gate SG. Memory cell MC is formed of a MOS transistor of a floating gate type.
The erase and write operations of the flash memory of the DINOR type will now be described below with reference to FIG. 49.
FIG. 49 shows a distribution of a threshold voltage of the memory cell in the DINOR-type flash memory using external power supply voltage Vcc of 3.3 V.
In the erase operation, electrons are injected into all the floating gate electrodes at a time by the FN tunneling phenomenon on the entire channel surface. Thereby, threshold voltage Vth changes from the lower threshold voltage side to the higher threshold voltage side.
In the write operation, electrons are extracted by the FN tunneling phenomenon at the drain edge. In the DINOR-type flash memory, therefore, the lower threshold voltage distribution side corresponds to the written state, and the higher threshold voltage distribution side corresponds to the erased state.
In the DINOR-type flash memory, the distribution in the lower threshold voltage side is narrowed by repeating such operations that a voltage in a pulse form is applied to extract electrons for one bit, and verification of the threshold voltage is performed. As a result, the lower limit of the distribution in the lower threshold voltage side goes to 1.5 V or more, and the operation using external power supply voltage of 3.3 V can be achieved.
There is a tendency to demand nonvolatile semiconductor memory devices, which can operate with a low voltage and/or low power consumption, and/or can perform fast reading.
A DINOR-type flash memory during a low-voltage operation suffers from a problem which will be described below with reference to FIG. 50.
As shown in FIG. 50, when external power supply voltage Vcc is of a value of 3.3 V or less (e.g., 1.8 V) which is now widely used, the lower limit of the threshold voltage at the lower side of the memory cell in the DINOR-type flash memory goes to 1.5 V or less so that an overwritten cell appears. As a result, it is probably difficult to achieve the read operation using external power supply voltage Vcc as it is, even if the above technology of the DINOR-type flash memory is utilized.
In order to overcome the above problem, such a manner can be envisaged that lowered external power supply voltage Vcc is boosted to a voltage level of or near the currently used value (3.3 V) during the read operation, and the boosted voltage is applied to the word line.
If this manner is employed, however, the reading operation requires a long time due to a time for boosting. Also, the boosting increases a power consumption. Further, circuits operating with 3.3 V increase in number, and this reduces an effect of lower power consumption which can be achieved by lowering the voltage to 1.8 V.
Accordingly, an object of the invention is to provide a nonvolatile semiconductor memory device which can avoid a malfunction due to overerasing or overwriting even in a low-voltage operation.
Another object of the invention is to provide a nonvolatile semiconductor memory device which can perform a fast read operation even with a low-voltage power supply.
Yet another object of the invention is to provide a nonvolatile semiconductor memory device which can operate with a low voltage and can be manufactured at a low cost.